In a switch which stripes data to a variable number of fabrics, a different physical bus topology is used if the speed of the input port changes. The mapping of the bits onto the backplane busses needs to maintain the following properties:                a. Optimal bandwidth utilization of the busses for all operating speeds (OC48 and OC192).        b. Support OC48/OC192 interoperability.        c. Utilize the same physical backplane busses for all speeds of operation.        
The present invention allows a design to be optimized for both OC48 and OC192 while maintaining compatibility between the two port speeds on the backplane. This allows one backplane design to support exchanging traffic between OC48 and OC192 ports.